MC68HC55 Datasheet, PDF (26/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

MC68HC55 Technical Data
Figure 4-6 describes the operation of the receive FIFO. State transitions
in this state machine occur at the trailing edges of R_FIFO_PUSH and
R_FIFO_POP. The receive FIFO is four levels deep, including the stage
which receives serial data from the current DSI transfer and the stage
that is accessible for SPI reads. To assure coherence of data and status,
each FIFO stage includes an extra bit for the CRC error status for each
received data word. Also for coherency, the DSI transfer state machine
imposes a delay at the end of a DSI transfer to assure that the CRC
status is stable before issuing the R_FIFO_PUSH request. The
RX_IDLE state is asynchronously entered at system reset, when the
enable bit goes low, or when there is an abort.
~EN or ABORT or RESET/
R_PUSH_PTR = 0
R_POP_PTR = 0
R_FIFO_EMPTY = TRUE
STATE TRANSITIONS OCCUR
ON THE TRAILING EDGES OF
R_FIFO_PUSH AND R_FIFO_POP
R_FIFO_POP &
(R_POP_PTR = R_PUSH_PTR – 1)/
R_POP_PTR = X_POP_PTR+1
R_FIFO_EMPTY = TRUE
RX_IDLE
R_FIFO_PUSH/
R_PUSH_PTR = R_PUSH_PTR+1
R_FIFO_EMPTY = FALSE
R_FIFO_POP &
(R_POP_PTR != R_PUSH_PTR – 1)/
R_POP_PTR = R_POP_PTR+1
RX_NOT_EMPTY
R_FIFO_PUSH &
(R_PUSH_PTR != R_POP_PTR – 1)/
R_PUSH_PTR = R_PUSH_PTR+1
R_FIFO_POP/
R_POP_PTR = R_POP_PTR+1
OVERFLOW = FALSE
R_FIFO_PUSH &
(R_PUSH_PTR = R_POP_PTR – 1)/
R_PUSH_PTR = R_PUSH_PTR+1
RX_FULL
Figure 4-6. State Diagram — Receive FIFO
During normal operation of the receive FIFO, values are pushed into the
FIFO from the DSI serial interface, causing the push pointer to
increment. After the SPI has read a data word, the receive FIFO is
popped, which makes the location available for additional data from the
DSI interface (it is the user’s responsibility to read status and data within
the same burst to assure coherence). The RX_NOT_EMPTY state is
active as long as there is some data in the FIFO.
Technical Data
26
MC68HC55
Functional Description