MC68HC55 Datasheet, PDF (23/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

MC68HC55 Technical Data
Enable (Disable) Function
RESET, ABORT, or ~EN/
DSIF = 1, DSIS = 1
RESET DELAY-CNTR
STATE TRANSITIONS OCCUR
ON POSEDGE OF SCALED SCLK
WAIT_FRAME_DELAY
DELAY_OVER &
X_FIFO NOT_EMPTY/
DSIF = 0
WAIT-SIGNAL_DLY0...2 CAUSES 1 BIT-TIME DELAY TO FIRST BIT FALLING EDGE
WAIT_SIGNAL_DLY_0
WAIT_SIGNAL_DLY_1
WAIT_SIGNAL_DLY_2
DSI_BIT_PNTR = 11 or 19
DSIS = 0
DSIS=DSI_DATA_OUT
DSIS = 1
~DSI_LAST_CRC_BIT/
DSI_BIT_PNTR = DSI_BIT_PNT – ;
DSIS = 0
TRANSFER_DSI_BITS_0
TRANSFER_DSI_BITS_1
TRANSFER_DSI_BITS_2
X_FIFO_POP = 0
DSI_X_POP
DSI_R_PUSH
R_FIFO_PUSH = 0
DSI_LAST_CRC_BIT/
DSIF = 1, DSIS = 1
RESET DELAY-CNTR
R_FIFO_PUSH = 1, X_FIFO_POP = 1
Figure 4-4. State Diagram — DSI Transfer
When enable is true and there is at least one valid entry in the transmit
FIFO, the DSI frame signal is driven low to start a frame. States
WAIT_SIGNAL_DLY_0 through WAIT_SIGNAL_DLY_2 create a one
DSI bit-time delay before the start of the first data bit. After
WAIT_SIGNAL_DLY_2, the DSI_BIT_PTR gets initialized to 11 or 19
(depending upon the value in the MSx control bit), and the
TRANSFER_DSI_BITS_0 state is entered.
TRANSFER_DSI_BITS_0 through TRANSFER_DSI_BITS_2 form a
loop where each pass corresponds to one DSI bit time. During the first
third of the bit, the DSIxS pin is low; during the second third, DSIxS is
low for a 0 or high for a 1; during the last third of the bit time, DSIxS is
high. Provided this is not the end of the last CRC bit, the bit pointer is
decremented and the loop is repeated.
MC68HC55
Functional Description
Technical Data
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