MC68HC55 Datasheet, PDF (16/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

MC68HC55 Technical Data
frame to the beginning of the next frame. The length of a bit time
depends upon the SCLK input frequency and the current setting in the
CDIV1[B:A] bits.
Table 3-5. DLY1 Frame Spacing Information
DLY1[B:A]
0:0
0:1
1:0
1:1
Minimum Delay between Frames
(Bit Times)
4
8
16
32
RIE1 — Receive Interrupt Enable (Channel 1) Bit
0 = Receive interrupt disabled; RFNE1 status does not affect INT
pin.
1 = Receive interrupt enabled; whenever the RFNE1 status flag is
1, the INT pin will be low to request an interrupt
TIE1 — Transmit Interrupt Enable (Channel 1) Bit
0 = Transmit interrupt disabled; TFE1 status does not affect INT
pin.
1 = Transmit interrupt enabled; whenever the TFE1 status flag is 1,
the INT pin will be low to request an interrupt
MS1 — Message Size (Channel 1) Bit
0 = 16 data bits plus 4 CRC bits data bits 15 through 0 then 4 CRC
bits
1 = 8 data bits plus 4 CRC bits data bits 7 through 0 then 4 CRC bits
If the DSI1CTRL register is written while a transfer is in progress, the
transfer is aborted without being completed.
Technical Data
16
MC68HC55
Registers and Bit Descriptions