MC68HC55 Datasheet, PDF (24/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

MC68HC55 Technical Data
After the last CRC bit, the DSI_R_PUSH state is entered. This state
ensures that the CRC flag is stable prior to adjusting the receive (and
transmit) FIFO pointers. The DSI_X_POP state prevents an
X_FIFO_POP from occurring at the same time as an R_FIFO_PUSH.
After DSI_X_POP, the state transitions back to the
WAIT_FRAME_DELAY state. This state ensures proper frame spacing
is allowed to charge up the storage capacitors in remote nodes. Notice
that the delay counter was reset at the end of the last CRC bit so the
delay period can start to time out even while the DSI_R_PUSH and
DSI_X_POP states are being processed.
Figure 4-5 describes the operation of the transmit FIFO. This FIFO is
four levels deep, including the stage which is written into by the SPI and
the stage which provides the data for the current DSI serial transfer.
State transitions in this state machine occur at the trailing edges of
X_FIFO_PUSH and X_FIFO_POP.
~EN or ABORT or RESET/
X_PUSH_PTR = 0
X_POP_PTR = 0
X_FIFO_EMPTY = TRUE
STATE TRANSITIONS OCCUR
ON THE TRAILING EDGES OF
X_FIFO_PUSH AND X_FIFO_POP
X_FIFO_POP &
(X_POP_PTR = X_PUSH_PTR –1)/
X_POP_PTR = X_POP_PTR+1
X_FIFO_EMPTY = TRUE
TX_IDLE
X_FIFO_PUSH/
X_PUSH_PTR = X_PUSH_PTR+1
X_FIFO_EMPTY = FALSE
X_FIFO_POP &
(X_POP_PTR != X_PUSH_PTR –1)/
X_POP_PTR = X_POP_PTR+1
TX_NOT_EMPTY
X_FIFO_PUSH &
X_PUSH_PTR != X_POP_PTR –1/
X_PUSH_PTR = X_PUSH_PTR+1
X_FIFO_POP/
X_POP_PTR = X_POP_PTR+1
X_FIFO_PUSH &
X_PUSH_PTR = X_POP_PTR –1/
X_PUSH_PTR = X_PUSH_PTR+1
TX_FULL
Figure 4-5. State Diagram — Transmit FIFO
Technical Data
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MC68HC55
Functional Description