MC68HC55 Datasheet, PDF (19/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

MC68HC55 Technical Data
Reset Function
SCLK
RESET
INT
CLK
DO
CS
DI
MC68HC55 — DISTRIBUTED SYSTEM INTERFACE — DIGITAL PORTION
CLOCK DIVIDERS
DIV BY 1, 2, 4, or 8
SCALED SCLKs
SPI
INTERRUPT
STATUS REG
CONTROL REGS
ENABLE REG
REG POINTER
BIT POINTER
ER0
DATA ¹⁶
POP
1
DATA
PUSH
ENx
ABORT
SPI_LAST_BIT
Rx FIFO
DATA
ER
DATA
ER
DATA
ER
DATA
ER
Tx FIFO
DATA
DATA
DATA
DATA
DATA
PUSH
DATA
POP
DSI0
CRC GENERATION
CRC CHECKING
16
DSI_XFER_0
SPI_XFER
ER1
DATA ¹⁶
POP
DATA ¹
PUSH
Rx FIFO
DATA
ER
DATA
ER
DATA
ER
DATA
ER
Tx FIFO
DATA
DATA
DATA
DATA
DATA
PUSH
DATA
POP
DSI1
CRC GENERATION
CRC CHECKING
16
DSI_XFER_1
DSI0R
DSI0S
DSI0F
DSI1R
DSI1S
DSI1F
Figure 4-1. MC68HC55 Block Diagram
4.1 Reset Function
A low level on RESET forces all FIFO bits to be cleared. The receive and
transmit FIFO pointers are cleared, which effectively forces the FIFOs to
the empty condition. Since the DSI channels are disabled (ENx = 0), the
DSIxF pins are high and the DSIxS pins are low, which forces the DSI/P
devices to three-state their bus outputs.
Reset also forces all MC68HC55 state machines to their idle state.
MC68HC55
Functional Description
Technical Data
19