MC68HC55 Datasheet, PDF (10/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

MC68HC55 Technical Data
3.2 DSI Channel 1 Data Registers
Address: $010
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIt 15
14
13
Write:
12
11
10
9
Bit 8
Reset: 0
0
0
0
0
0
0
0
Figure 3-3. DSI Channel 1 Data Register Upper Byte (DSI1H)
Address: $011
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIt 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 3-4. DSI Channel 1 Data Register Lower Byte (DSI1L)
For the description of DSI1H and DSI1L, refer to 3.1 DSI Channel 0
Data Registers.
3.3 DSI Status Register
Address:
Read:
Write:
Reset:
$100
Bit 7
6
5
4
3
2
1
ER1 TFE1 TFNF1 RFNE1 ER0 TFE0 TFNF0
0
1
1
0
0
1
1
= Unimplemented
Figure 3-5. DSI Status Register (DSISTAT)
Bit 0
RFNE0
0
This 8-bit register provides status information for both channels of the
DSI/D. A copy of this register is latched at the falling edge of the SPI chip
select to avoid asynchronous problems due to bits changing during an
SPI transfer. Any changes that occur while chip select remains low (due
to SPI data reads or writes or reception of new DSI data, etc.) will not be
Technical Data
10
MC68HC55
Registers and Bit Descriptions