MC68HC55 Datasheet, PDF (36/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

MC68HC55 Technical Data
5.4 Timing Characteristics for SPI Interface
The table and Figure 5-2 describe AC timing characteristics of the SPI
pins. This timing is compatible with a Freescale SPI system that is set up
as a master with CPHA = CPOL = 0. Figure 5-3 is a general timing
diagram for a single SPI transfer.
Parameter⁽¹⁾
Symbol Min
Typ
Max
Units
SPI clock frequency
SPI clock cycle time
SPI clock high time
SPI clock low time
SPI CS lead time
SPI CS lag time
Data setup time
DI valid before CLK rising edge
f_SPI
0
—
4
MHz
t_CYC
227
—
—
ns
t_HI
91
125
—
ns
t_LO
91
125
—
ns
t_Lead
227
—
—
ns
t_Lag
227
—
—
ns
t_SU
25
—
—
ns
Data hold time
DI valid after CLK rising edge
DO valid after CLK falling edge
Access time
CS fall to DO valid
t_H
25
—
—
ns
t_HO
0
—
—
t_A
—
—
100
ns
Data valid time
CLK falling edge to DO valid
t_V
—
—
100
ns
Output disable time
CS rise to DO Hi-Z
t_DIS
—
—
100
ns
Rise time (20% V_DD to 70% V_DD)
CLK, DO
t_R
—
—
25
ns
Fall time (70% V_DD to 20% V_DD)
CLK, DO
t_F
—
—
25
ns
1. 4.5 volts ≤ V_DD ≤ 5.5 volts; –40°C ≤ T_AMB ≤ 85°C; C ≤ 200 pF load on all SPI pins
Technical Data
36
MC68HC55
Timing and Electrical Specifications