MC68HC55 Datasheet, PDF (17/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

3.5 DSI Channel Enable Bits
MC68HC55 Technical Data
DSI Channel Enable Bits
Address: $111
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
EN1
EN0
Write:
Reset:
0
0
Figure 3-8. DSI Channel Enable Bits (DSIENABLE)
This read/write register is used to enable or disable each DSI channel.
When a DSI channel is disabled, its DSIxF pin is high and its DSIxS pin
is low which forces the DSI/P device to three-state its bus outputs.
Disabling a DSI channel clears the transmit and receive FIFOs for that
channel. See 4.3 Enable (Disable) Function.
NOTE: Bits [7:2] are reserved and read as 0s. These bits could be used in future
versions of the MC68HC55.
EN1 — Enable for DSI Channel 1 Bit
0 = DSI channel 1 disabled;
DSI1F pin = high (1), DSI1S pin = low (0)
1 = DSI channel 1 enabled; operates normally
EN0 — Enable for DSI Channel 0 Bit
0 = DSI channel 0 disabled;
DSI0F pin = high (1), DSI0S pin = low (0)
1 = DSI channel 0 enabled; operates normally
MC68HC55
Registers and Bit Descriptions
Technical Data
17