MC68HC55 Datasheet, PDF (29/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

MC68HC55 Technical Data
DSI/D to DSI/P Communications
Although it looks like the read and write for an address are occurring at
the same time, the changes caused by the write are not reflected in the
read that is taking place during the same SPI transfer. Also, if the burst
were extended such that it read status again, the status changes caused
earlier during the same burst would not be reflected (status is latched at
chip select fall).
4.5 DSI/D to DSI/P Communications
DSI/D to DSI/P communications involve a frame (DSIxF), a data signal
(DSIxS), and a data return (DSIxR) signal. This ASIC device supports
two independent channels of DSI communications and is used with a
matching 2-channel analog SmartMOS device called the DSI/P. All
DSI/D to DSI/P communications are initiated by the DSI/D in response
to register writes within the DSI/D which in turn are controlled by
commands received through the SPI.
Messages are eight or 16 bits of data (as controlled by the MSx bit in the
DSIxCTRL register) plus four bits of CRC, so messages contain 12 or 20
bits of information. CRC generation and checking are done in the DSI/D.
A message starts with a falling edge on the DSIxF signal which marks
the start of a frame. There is a one bit-time delay before the MSB (most
significant bit) of data appears on the DSIxS pin. Data bits start with a
falling edge on DSIxS. The low time is one-third of the bit time for a 1 and
two-thirds of a bit time for 0. Data is transmitted on DSIxS and received
on DSIxR pins simultaneously. Receive data is the captured level on the
DSIxR pin at the end of each bit time. At the end of the bit time for the
last CRC bit, the DSIxF pin returns to a logic high (idle level). The DSI/D
imposes a minimum delay between successive frames of 4, 8, 16, or 32
bit times.
The user initiates a message by writing (via the SPI interface from the
MCU) to the low byte of the data register (DSIxL). When 16-bit
messages are to be sent, this allows the user to write the DSIxH register
and then the DSIxL register before the combined 16-bit data value
(DSIxH:DSIxL) is sent. The user should first check the TFNFx status flag
to be sure the transmit FIFO is not full before writing a new data value to
DSIxH and/or DSIxL. When the minimum inter-frame delay has been
MC68HC55
Functional Description
Technical Data
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