MC68HC55 Datasheet, PDF (12/40 Pages) Freescale Semiconductor, Inc – Two-Channel CMOS ASIC Device

MC68HC55 Technical Data
Technical Data
12
TFNF1 — Transmit FIFO Not Full Bit (Channel 1)
0 = Transmit FIFO full; no room to write any additional data
1 = FIFO not full; there is room for more data in the transmit FIFO
There is no interrupt associated with the transmit FIFO not full
condition. When the conclusion of a DSI transfer frame would cause
both TFNF and RFNE to become set, RFNE becomes set but TFNF
is not set until one DSI clock cycle later. When the transmit FIFO is
full, attempts to write more data into the FIFO are ignored.
RFNE1 — Receive FIFO Not Empty Bit (Channel 1)
0 = Receive FIFO empty; no new data ready to be read
1 = One or more data entries in receive FIFO; data is available to
be read
It is not possible to overflow the receive FIFO because it is not
possible to get more than four transmit messages into the system at
a time. When there is any data in the receive FIFO, a write to the
transmit buffer also reads (pops) data from the receive FIFO.
ER0 — CRC Error Bit (Channel 0 Read)
0 = CRC value for the data in the read buffer was correct.
1 = CRC value for the data in the read buffer was not correct (data
is not valid).
Refer to the description of ER1.
TFE0 — Transmit FIFO Empty Bit (Channel 0)
0 = Transmit FIFO not empty
1 = Transmit FIFO empty
Refer to the description of TFE1.
TFNF0 — Transmit FIFO Not Full Bit (Channel 0)
0 = Transmit FIFO full; no room to write any additional data
1 = FIFO not full; there is room for more data in the transmit FIFO
Refer to the description of TFNF1.
RFNE0 — Receive FIFO Not Empty Bit (Channel 0)
0 = Receive FIFO empty; no new data ready to be read
1 = One or more data entries in receive FIFO; data is available to
be read
Refer to the description of RFNE1.
MC68HC55
Registers and Bit Descriptions