MCIMX233CJM4B Datasheet, PDF (840/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

Data Co-Processor (DCP)
BITS
31:0 COUNT
Table 16-40. HW_DCP_PACKET5 Bit Field Descriptions
LABEL
RW RESET
RO 0x0
DEFINITION
Byte Count register. This value is the working value
and will update as the operation proceeds.
DESCRIPTION:
This register shows the contents of the bytecount register from the packet being processed. The field can
be considered either a byte count
or a buffer size. The logic treats this as a decrmenting count of bytes from the buffer size programmed into
the field. As the transaction
proceeds, the logic will decrement the bytecount as data is written to the destination buffer. For blit
operations, the top 16-bits of this field
represents the number of lines (y size) in the blit and the lower 16-bits represent the number of bytes in a
line (x size).
EXAMPLE:
Empty Example.
16.3.15 DCP Work Packet 6 Status Register Description
This register displays the values for the current work packet offset 0x1C (Payload Pointer) field.
HW_DCP_PACKET6
0x0E0
Table 16-41. HW_DCP_PACKET6
33222222222211111111110000000000
10987654321098765432109876543210
ADDR
BITS
31:0 ADDR
Table 16-42. HW_DCP_PACKET6 Bit Field Descriptions
LABEL
RW RESET
RO 0x0
DEFINITION
This regiser reflects the payload pointer for the current
control packet.
DESCRIPTION:
This register shows the contents of the payload pointer fieldr from the packet being processed.
EXAMPLE:
Empty Example.
16.3.16 DCP Channel 0 Command Pointer Address Register Description
The DCP channel 0 current command address register points to the multiword descriptor that is to be
executed (or currently being executed). The channel may be activated by writing the command pointer
address to a valid descriptor in memory and then updating the semaphore to a non-zero value. After the
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i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor