MCIMX233CJM4B Datasheet, PDF (184/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

Interrupt Collector
Table 5-137. HW_ICOLL_INTERRUPT58 Bit Field Descriptions
BITS
31:5 RSRVD1
4
ENFIQ
LABEL
3
SOFTIRQ
2
ENABLE
1:0 PRIORITY
RW RESET
RO 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
DEFINITION
Always write zeroes to this bitfield.
Set this to 1 to steer this interrupt to the non-vectored
FIQ line. When set to 0 the interrupt will pass through
the main IRQ FSM and priority logic.
DISABLE = 0x0 Disable
ENABLE = 0x1 Enable
Set this bit to one to force a software interrupt.
NO_INTERRUPT = 0x0 turn off the software interrupt request.
FORCE_INTERRUPT = 0x1 force a software interrupt
Enable the interrupt bit through the collector.
DISABLE = 0x0 Disable
ENABLE = 0x1 Enable
Set the priority level for this interrupt, 0x3 is highest,
0x0 is lowest (weakest).
LEVEL0 = 0x0 level 0, lowest or weakest priority
LEVEL1 = 0x1 level 1
LEVEL2 = 0x2 level 2
LEVEL3 = 0x3 level 3, highest or strongest priority
DESCRIPTION:
This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this
register controls the enable and software generated interrupt. WARNING: Modifying the priority of an
enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to
changing its priority.
EXAMPLE:
HW_ICOLL_INTERRUPT58_SET(0,0x00000001);
5.4.69 Interrupt Collector Interrupt Register 59 Description
This register provides a mechanism to specify the priority level for an interrupt source. It also provides an
enable and software interrupt for each one, as well as security designation.
HW_ICOLL_INTERRUPT59
HW_ICOLL_INTERRUPT59_SET
HW_ICOLL_INTERRUPT59_CLR
HW_ICOLL_INTERRUPT59_TOG
0x4D0
0x4D4
0x4D8
0x4DC
Table 5-138. HW_ICOLL_INTERRUPT59
33222222222211111111110000000000
10987654321098765432109876543210
5-76
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor