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MCIMX233CJM4B Datasheet, PDF (1211/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual
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AUDIOOUT/DAC
lation filter to the sigma delta modulator corresponding to every 8.503 FanalogDAC samples. Recall that
this is a variable rate interpolation stage that changes for every Over Sample Rate (OSR) setting in use.
If the desired sample rate FsampleDAC= 44.1 kHz, for example, the sample hold and interpolate block
will accept samples from fixed interpolation filter at 352.8 kHz, i.e., 8x the desired sample rate. There is
a handshake pair (request/ack) between the variable rate sample hold and interpolate block and the fixed
interpolating filter block. This handshake is used to pace the samples from the FIFO to 44.1 kHz.
Handshake
Right Channel
from DMA
3D Effect
1 x FsampleDAC 8 x FsampleDAC
1:8 Fixed
Interp. Filter
Sample Hold
& Interpolate
Sigma
Delta
dac_rsamp 1-Bit R
Analog
Modulator
D/A
Handshake
Left Channel
from DMA
3D Effect
1:8 Fixed
Interp. Filter
Sample Hold
& Interpolate
Sigma
Delta
dac_lsamp 1-Bit L
Analog
Modulator
D/A
HW_AUDIOOUT_ANACLKCTRL_DACDIV
24.0 MHz
XTAL
OSC
÷DA_DIV
samp_strobe
XTAL_CLK
FanalogDAC
position_reg[31:0]
HW_AUDIOOUT_DACSRR
24'hFF0000
+1
1
31
16 15
samp_strobe
Position Reg
whole fraction
#
pos_zero=
(position_reg[23:16] == 8'h00)
Variable Rate Interpolator
frac[15:0]
pos_zero
Figure 29-3. Stereo Sigma Delta D/A Converter
There are also members of the 48-kHz family whose members satisfy the property:
24.576 MHz = Q * FsampleDAC
These sample rates include 48 kHz, 32 kHz, 24 kHz, 16 kHz, and 12 kHz.
There are also the members of the 44.1-kHz family whose members satisfy the property:
16.9344 MHz = Q * FsampleADC
where Q comes from the set of integers. These sample rates include 44.1 kHz, 22.05 kHz, and 11.025
kHz.
The D/A converter block includes a variable rate or rational interpolator to accommodate these sample
rates, as shown in Figure 29-3. Rational numbers in the DAC are approximated with a scaled fixed-point
24-bit value. In this case, the decimal point falls between bit 15 and bit 16. Therefore, the lower two bytes
Freescale Semiconductor
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
29-7
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