MCIMX233CJM4B Datasheet, PDF (375/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

USB High-Speed Host/Device Controller
how many ports need service. This register is only reset when power is initially applied or in response to
a controller reset. The initial conditions of a port are: - No device connected - Port disabled If the port has
port power control, this state remains until software applies power to the port by setting port power to 1.
Device Controller: A device controller must implement only port register 1 and it does not support power
control. Port control in device mode is only used for status port reset, suspend, and current connect status.
It is also used to initiate test mode or force signaling and allows software to put the PHY into low power
suspend mode and disable the PHY clock. * Default Value: 00010000000000000000XX0000000000b
(Host mode) 00010000000000000001XX0000000100b (Device mode) X = Unknown
HW_USBCTRL_PORTSC1
0x184
Table 8-63. HW_USBCTRL_PORTSC1
33222222222211111111110000000000
10987654321098765432109876543210
BITS
31:30 PTS
29 STS
28 PTW
27:26 PSPD
25 SRT
24 PFSC
Table 8-64. HW_USBCTRL_PORTSC1 Bit Field Descriptions
LABEL
RW RESET
RW 0x0
RW 0x0
RW 0x1
RW 0x0
RW 0x0
RW 0x0
DEFINITION
Parallel Transceiver Select.
For this implementation, always set to 00b for UTMI.
UTMI = 0 UTMI/UTMI+.
PHIL = 1 Phillips-Classic.
ULPI = 2 ULPI.
SERIAL = 3 Serial/1.1FS.
Serial Transceiver Select.
Always 0.
Parallel Transceiver Width.
This bit is always 0, indicating an 8-bit (60-MHz) UTMI
interface.
Port Speed.
This register field indicates the speed at which the port
is operating. For high-speed mode operation in the
host controller and high-speed/fullspeed operation in
the device controller, the port routing steers data to the
protocol engine.
This bit is not defined in the EHCI specification.
FULL = 0 Full Speed.
HIGH = 2 High Speed.
Reserved.
Port Force Full Speed Connect.
Default = 0.
Writing this bit to a 1 will force the port to only connect
at Full Speed. It disables the chirp sequence that
allows the port to identify itself as high-speed. This is
useful for testing full-speed configurations with a
high-speed host, hub or device.
This bit is not defined in the EHCI specification. This bit
is for debugging purposes.
Freescale Semiconductor
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-43