MCIMX233CJM4B Datasheet, PDF (315/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

On-Chip OTP (OCOTP) Controller
DESCRIPTION:
Shadowed memory mapped access to OTP bank 1, word 0 (ADDR = 0x08).
EXAMPLE:
Empty Example.
7.4.12 HW Capability Shadow Register 1 Description
Copied from the OTP automatically after reset. Can be re-loaded by setting
HW_OCOTP_CTRL[RELOAD_SHADOWS]
HW_OCOTP_HWCAP1
0x0B0
Table 7-23. HW_OCOTP_HWCAP1
33222222222211111111110000000000
10987654321098765432109876543210
BITS
BITS
31:0 BITS
Table 7-24. HW_OCOTP_HWCAP1 Bit Field Descriptions
LABEL
RW RESET
RW 0x0
DEFINITION
Shadow register for HW capability bits 63:32 (copy of
OTP bank 1, word 1 (ADDR = 0x09)). These bits
become read-only after the
HW_OCOTP_LOCK[HWSW_SHADOW] or
HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is
set.
DESCRIPTION:
Shadowed memory mapped access to OTP bank 1, word 1 (ADDR = 0x09).
EXAMPLE:
Empty Example.
7.4.13 HW Capability Shadow Register 2 Description
Copied from the OTP automatically after reset. Can be re-loaded by setting
HW_OCOTP_CTRL[RELOAD_SHADOWS]
HW_OCOTP_HWCAP2
0x0C0
Table 7-25. HW_OCOTP_HWCAP2
33222222222211111111110000000000
10987654321098765432109876543210
BITS
Freescale Semiconductor
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
7-15