MCIMX233CJM4B Datasheet, PDF (470/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

AHB-to-APBH Bridge with DMA
Table 10-80. HW_APBH_CH4_DEBUG2
33222222222211111111110000000000
10987654321098765432109876543210
Table 10-81. HW_APBH_CH4_DEBUG2 Bit Field Descriptions
BITS
LABEL
31:16 APB_BYTES
15:0 AHB_BYTES
RW RESET
RO 0x0
RO 0x0
DEFINITION
This value reflects the current number of APB bytes
remaining to be transfered in the current transfer.
This value reflects the current number of AHB bytes
remaining to be transfered in the current transfer.
DESCRIPTION:
This register allows debug visibility of the APBH DMA Channel 4.
EXAMPLE:
Empty example.
10.5.40 APBH DMA Channel 5 Current Command Address Register
Description
The APBH DMA Channel 5 current command address register points to the multiword command that is
currently being executed. Commands are threaded on the command address.
HW_APBH_CH5_CURCMDAR
0x270
Table 10-82. HW_APBH_CH5_CURCMDAR
33222222222211111111110000000000
10987654321098765432109876543210
CMD_ADDR
Table 10-83. HW_APBH_CH5_CURCMDAR Bit Field Descriptions
BITS
LABEL
31:0 CMD_ADDR
RW RESET
RO 0x00000000
DEFINITION
Pointer to command structure currently being
processed for channel 5.
DESCRIPTION:
APBH DMA Channel 5 is controlled by a variable sized command structure. This register points to the
command structure currently being executed.
10-50
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor