MCIMX233CJM4B Datasheet, PDF (729/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

8-Symbol Correcting ECC Accelerator (ECC8)
When the data is read from the NAND by the GPMI, it is passed to the ECC8. Inside the ECC8, the data
is copied to the payload buffer or auxiliary buffer using the AHB bus master in the ECC8. The ECC8
needs some work space in system memory to hold intermediate results. These elements are allocated in
the auxiliary buffer pointed to by HW_GPMI_AUXILIARY.
Notice that programming the ECC8 for NAND reads consists largely of removing the soft reset and clock
gates from HW_ECC8_CTRL and clearing the HW_ECC8_CTRL_COMPLETE_IRQ, since most of the
actual programming is accomplished through PIO operations included in GPMI DMA command struc-
tures.
Set HW_ECC8_CTRL_COMPLETE_IRQ_EN to one, then start the GPMI’s DMA, and let it run. The
ECC8 interrupts the CPU after completing the entire transaction. This could be a single 512-byte block if
desired or the entire 4K page of payload data and the 65 bytes of metadata. It also could be just the meta-
data block. Note that the metadata is protected by its own 9-byte parity so that reading metadata is very
efficient.
The ECC8 status registers indicate the quality of the data read into each of the nine blocks with a four-bit
code.
• A value of 0 means no errors occurred on the block.
• A value of 1–8 means that correctable errors occurred but the data was repaired by the bus master.
• A value of 0xC means that this block was not specified on the read transaction.
• A value of 0xE means that an uncorrectable error occurred on that block.
• A value of 0xF means that this block contains all ones and is therefore considered to be an
ERASED block.
• A summary status quickly tells if any block in the page had an uncorrectable error.
14.2.2 Reed-Solomon ECC Encoding for NAND Writes
The RS encoder flowchart in Figure 14-6 shows the detailed steps involved in programming and using
the ECC8 encoder. This flowchart shows how to use the ECC8 block with the GPMI.
To use the ECC8 encoder with the GPMI’s DMA, create a DMA command chain containing ten descrip-
tor structures, as shown in Figure 14-8 and detailed in the DMA structure code example that follows it in
Section 14.2.2.1, “DMA Structure Code Example.” The ten descriptors perform the following tasks:
1. Disable the ECC8 block (in case it was enabled) and issue NAND write setup command byte
(under “CLE”) and address bytes (under “ALE”).
2. Configure and enable the ECC8 block and write the data payload.
3. Write the auxiliary payload.
4. Disable the ECC8 block and issue NAND write execute command byte (under “CLE”).
5. Wait for the NAND device to finish writing the data by watching the ready signal.
6. Check for NAND timeout via “DMA_SENSE”. Refer to Section 10.2 for a description of DMA
SENSE.
Freescale Semiconductor
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
14-11