MCIMX233CJM4B Datasheet, PDF (105/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

Clock Generation and Control
Table 4-35. HW_CLKCTRL_CLKSEQ Bit Field Descriptions
BITS
LABEL
31:9 RSRVD1
8
BYPASS_ETM
7
BYPASS_CPU
6
BYPASS_EMI
5
BYPASS_SSP
4
BYPASS_GPMI
3
BYPASS_IR
2
RSRVD0
1
BYPASS_PIX
0
BYPASS_SAIF
RW RESET
RO 0x0
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RO 0x0
RW 0x1
RW 0x1
DEFINITION
Always set to zero (0).
ETM bypass select. 1 = Select ref_xtal path to
generate the ETM clock domain. 0 = Select ref_cpu
path to generate the ETM clock domain. PLL and
9-phase fractional divider must be configured when
this bit is cleared.
CPU bypass select. 1 = Select ref_xtal path to
generate the CPU and APBH clock domains. 0 =
Select ref_cpu path to generate the CPU and APBH
clock domains. PLL and 9-phase fractional divider
must be configured when this bit is cleared.
EMI bypass select. 1 = Select ref_xtal path to generate
the EMI clock domain. 0 = Select ref_emi path to
generate the EMI clock domain. PLL and 9-phase
fractional divider must be configured when this bit is
cleared.
SSP bypass select. 1 = Select ref_xtal path to
generate the SSP clock domain. 0 = Select ref_io path
to generate the SSP clock domain. PLL and 9-phase
fractional divider must be configured when this bit is
cleared.
GPMI bypass select. 1 = Select ref_xtal path to
generate the GPMI clock domain. 0 = Select ref_io
path to generate the GPMI clock domain. PLL and
9-phase fractional divider must be configured when
this bit is cleared.
IR bypass select. 1 = Select ref_xtal path to generate
the IR clock domain. 0 = Select ref_io path to generate
the IR clock domain. PLL and 9-phase fractional
divider must be configured when this bit is cleared.
Always set to zero (0).
PIX bypass select. 1 = Select ref_xtal path to generate
the PIX clock domain. 0 = Select ref_pix path to
generate the PIX clock domain. PLL and 9-phase
fractional divider must be configured when this bit is
cleared.
Reserved - Always set to zero (0) - Notice this is not
the reset value.
DESCRIPTION:
This register controls the selection of clock sources (ref_xtal or ref_*) for various clock dividers.
EXAMPLE:
HW_CLKCTRL_CLKSEQ_WR(BF_CLKCTRL_CLKSEQ_BYPASS_IR(1));
4.8.18 System Software Reset Register Description
The RESET control register provides control for soft reset.
HW_CLKCTRL_RESET
0x120
Freescale Semiconductor
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
4-29