MCIMX233CJM4B Datasheet, PDF (319/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

On-Chip OTP (OCOTP) Controller
Table 7-36. HW_OCOTP_CUSTCAP Bit Field Descriptions
BITS
LABEL
RW RESET
31 CUST_DISABLE_WMADRM9 RW 0x0
30 CUST_DISABLE_JANUSDRM RW 0x0
10
29:5 RSRVD1
RW 0x0
4
ENABLE_SJTAG_12MA_DRI RW 0x0
VE
3
USE_PARALLEL_JTAG
RW 0x0
2
RTC_XTAL_32768_PRESENT RW 0x0
1
RTC_XTAL_32000_PRESENT RW 0x0
0
RSRVD0
RW 0x0
DEFINITION
Blow to disable WMA DRM9.
Blow to disable WMA Janus DRM10.
Reserved - do not blow these bits.
Blow to force the 1-wire DEBUG (serial JTAG) pin to
drive 12mA, the default is 8mA (see
ENABLE_PJTAG_12MA_DRIVE in the ROM0 register
for 6-wire parallel JTAG). This is a hardware override
which will cause the drive select bits in the PINCTRL
block to reset to the 12mA drive settings rather than
the normal default of 8mA. The user is still free to
reprogram these bits to other drive levels.
During JTAG boot mode, the ROM reads this bit, then
inverts it, and writes the value to the
HW_DIGCTL_CTRL_USE_SERIAL_JTAG bit. If this
bit is one, indicating parallel JTAG mode is selected, a
zero is written to the DIGCTL USE_SERIAL_JTAG bit
which places the device into 6-wire JTAG mode, and if
this bit is zero, a one instead is written causing the
SJTAG block to switch to the 1-wire serial JTAG mode.
Blow to indicate the presence of an optional
32.768KHz crystal off-chip.
Blow to indicate the presence of an optional
32.000KHz crystal off-chip.
Reserved - do not blow these bits.
DESCRIPTION:
Shadowed memory mapped access to OTP bank 1, word 7 (ADDR = 0x0F).
EXAMPLE:
Empty Example.
7.4.19 LOCK Shadow Register OTP Bank 2 Word 0 Description
Shadow register for OCOTP Lock Status Value (ADDR = 0x10). Copy of the state of the OTP lock
regions. Copied from the OTP upon reset. Can be re-loaded by setting
HW_OCOTP_CTRL[RELOAD_SHADOWS]
HW_OCOTP_LOCK
0x120
Freescale Semiconductor
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
7-19