MCIMX233CJM4B Datasheet, PDF (84/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

Clock Generation and Control
When the carry out of the fractional count is one, a rising edge output pulse is initiated and the remainder
of the accumulator is preserved. The sub fractional accumulated value is considered to determine if the
output edge should occur on the falling edge of the reference clock or the rising edge of the reference
clock to minimize output clock jitter
4.3.2.1.1 Fractional ClockDivide Example, Divide by 3/8
This example uses a 3 bit fractional accumulator to divide the reference clock input by 3/8. There are 3
output clock edges produced for every 8 input reference clock edges. An output edge is generated on
every cycle that the fractional accumulator carries out of the most significant bit. Notice when the frac-
tional component is .01, the output edge is shifted and generated off the falling edge of the input refer-
ence clock. This is done to produce the best output duty cycle that can be achieved based on the input
reference clock frequency.
CLK_REF
3 output clocks repeats
every 8 reference clocks
3 bit divider
0.000 0.011 0.110 1.001 0.100 0.111 1.010 0.101 1.000 0.011
CLK_OUT
2^nd cycle on falling clk_ref
½ cycle shift
Figure 4-2. Fractional Clock divide; 3/8 example
4.3.3 Gated Clock Divide Mode
This mode is selected when the reference clock frequency is divided by a range of 1 < div < 2. To select
this mode, program the FRAC_EN field to logic 1 and progarm the DIV field with the most significant bit
set to logic 1. In this case, the reference clock is enabled/disabled on a cycle by cycle basis to pass to the
output clock domain. Essentially, the reference clock is gated on or off depending on the cary out bit of
the fractional count accumulator. This option is useful to divide the 24 MHz clock to a range between 12
to 24 MHz. The effective period is equal to the reference period since the output clock is a gated version
of the reference clock. For example, a divide value of 4/3 will allow 3 consecutive pulses of the reference
clock to propagate and will then gate off a single refer¬ence clock cycle. The edge to edge timing is
effectively equal to the reference clock.
i.MX23 Applications Processor Reference Manual, Rev. 1
4-8
Freescale Semiconductor
Preliminary—Subject to Change Without Notice