MCIMX233CJM4B Datasheet, PDF (497/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

AHB-to-APBX Bridge with DMA
The NO_DMA_XFER command is used to write PIO words to a device without performing any DMA
data byte transfers.
As each DMA command completes, it triggers the DMA to load the next DMA command structure in the
chain. The normal flow list of DMA commands is found by following the NEXTCMD_ADDR pointer in
the DMA command structure. If the wait-for-end-command bit (WAIT4ENDCMD) is set in a command
structure, then the DMA channel will wait for the device to signal completion of a command by toggling
the apx_endcmcd signal before proceeding to load and execute the next command structure. The sema-
phore is decremented after the end command is seen.
A detailed bit-field view of the DMA command structure is shown in Table 11-3, which shows a field that
specifies the number of bytes to be transferred by this DMA command. The transfer count mechanism is
duplicated in the associated peripheral, either as an implied or specified count in the peripheral.
Table 11-3. DMA Channel Command Word in System Memory
33222222222211111111110000000000
10987654321098765432109876543210
NEXT_COMMAND_ADDRESS
Number DMA Bytes to Transfer
Number PIO
Words to
Write
Reserved
DMA Buffer or Alternate CCW
Zero or More PIO Words to Write to the Associated Peripheral Starting at its Base Address on the APBX Bus
Figure 11-3 shows the CHAIN bit in bit 2 of the second word of the command structure. This bit is set to
1 if the NEXT_COMMAND_ADDRESS contains a pointer to another DMA command structure. If a
null pointer (0) is loaded into the NEXT_COMMAND_ADDRESS, it will not be detected by the DMA
hardware. Only the CHAIN bit indicates whether a valid list exists beyond the current structure.
If the IRQ_COMPLETE bit is set in the command structure, then the last act of the DMA before loading
the next command is to set the interrupt status bit corresponding to the current channel. The sticky inter-
rupt request bit in the DMA CSR remains set until cleared by software. It can be used to interrupt the
CPU.
Each channel has an eight-bit counting semaphore that controls whether it is in the run or idle state. When
the semaphore is non-zero, the channel is ready to run and process commands and DMA transfers. When-
ever a command finishes its DMA transfer, it checks the DECREMENT_SEMAPHORE bit. If set, it dec-
rements the counting semaphore. If the semaphore goes to 0 as a result, then the channel enters the IDLE
state and remains there until the semaphore is incremented by software. When the semaphore goes to
Freescale Semiconductor
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
11-5