MCIMX233CJM4B Datasheet, PDF (371/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

USB High-Speed Host/Device Controller
Table 8-54. HW_USBCTRL_TXFILLTUNING Bit Field Descriptions
BITS
LABEL
12:8 TXSCHEALTH
7
RSVD0
6:0 TXSCHOH
RW RESET
RW 0x0
RO 0x0
RW 0x0
DEFINITION
Scheduler Health Counter.
This register increments when the host controller fails
to fill the TX latency FIFO to the level programmed by
TXFIFOTHRES before running out of time to send the
packet before the next Start-Of-Frame.
This health counter measures the number of times this
occurs to provide feedback to selecting a proper
TXSCHOH. Writing to this register will clear the
counter and this counter will max. at 31.
Reserved.
This bit is reserved and its value has no effect on
operation.
Scheduler Overhead.
This register adds an additional fixed offset to the
schedule time estimator described above as Tff. As an
approximation, the value chosen for this register
should limit the number of back-off events captured in
the TXSCHHEALTH to less than 10 per second in a
highly utilized bus. Choosing a value that is too high for
this register is not desired as it can needlessly reduce
USB utilization.
The time unit represented in this register is 1.267us
when a device is connected in High-Speed Mode for
OTG & SPH.
The time unit represented in this register is 6.333us
when a device is connected in Full Speed Mode for
OTG & SPH.
The time unit represented in this register is always
1.267 in the MPH product.
DESCRIPTION:
TX Fill Tuning
EXAMPLE:
Empty Example.
8.6.28 Inter-Chip Control Register Description
This register is present but not used in this implementation.
HW_USBCTRL_IC_USB
0x16c
Table 8-55. HW_USBCTRL_IC_USB
33222222222211111111110000000000
10987654321098765432109876543210
Freescale Semiconductor
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-39