MCIMX233CJM4B Datasheet, PDF (24/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

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DRAM Controller AHB Address Breakdown ...................................................................... 12-2
DRAM Controller Architecture ............................................................................................ 12-3
Memory Controller Memory Map: Maximum...................................................................... 12-4
Example Memory Map: 10 Row Bits, 11 Column Bits ........................................................ 12-5
DQS Read Timing................................................................................................................. 12-7
DQS Gating........................................................................................................................... 12-8
DRAM DQS Arrival Time Requirements............................................................................. 12-9
DQS Write Timing .............................................................................................................. 12-10
Write Data and DQS Relationship ...................................................................................... 12-10
Write Data with Programmable Delays .............................................................................. 12-11
WR_DQS_SHIFT Delay Setting Example ......................................................................... 12-11
DRAM Clock Programmable Delay ................................................................................... 12-12
General-Purpose Media Interface Controller Block Diagram .............................................. 13-2
BASIC NAND Flash Timing ................................................................................................ 13-4
NAND Flash Read Path Timing ........................................................................................... 13-5
NAND Flash Command and Address Timing Example ....................................................... 13-6
Hardware 8-Symbol Correcting ECC Accelerator (ECC8) Block Diagram......................... 14-3
ECC-Protected 2K NAND Page Data—NAND Memory Footprint .................................... 14-5
ECC-Protected 2K NAND Page Data—System Memory Footprint .................................... 14-6
ECC-Protected 4K NAND Page Data—NAND Memory Footprint .................................... 14-7
ECC-Protected 4K NAND Page Data—System Memory Footprint .................................... 14-8
ECC8 Reed-Solomon Encode Flowchart............................................................................ 14-12
ECC8 DMA Descriptor Legend.......................................................................................... 14-13
ECC8 Reed-Solomon Encode DMA Descriptor Chain ...................................................... 14-14
ECC8 Reed-Solomon Decode Flowchart ........................................................................... 14-20
ECC8 Reed-Solomon Block Coding—Decoder for t=8 ..................................................... 14-21
ECC8 Reed-Solomon Decode DMA Descriptor Chain...................................................... 14-22
Hardware BCH Accelerator .................................................................................................. 15-3
Block Pipeline while Reading Flash ..................................................................................... 15-4
FLASH Page Layout Options ............................................................................................... 15-5
BCH Data Buffers in Memory .............................................................................................. 15-8
Memory-to-Memory Operations........................................................................................... 15-9
BCH Encode Flowchart ...................................................................................................... 15-11
BCH DMA Descriptor Legend ........................................................................................... 15-11
BCH Encode DMA Descriptor Chain................................................................................. 15-12
BCH Decode Flowchart ...................................................................................................... 15-18
BCH Decode DMA Descriptor Chain ................................................................................ 15-20
Data Co-Processor (DCP) Block Diagram............................................................................ 16-1
Cipher Block Chaining (CBC) Mode Encryption................................................................. 16-6
Cipher Block Chaining (CBC) Mode Decryption................................................................. 16-7
DCP Arbitration .................................................................................................................... 16-8
i.MX23 Applications Processor Reference Manual, Rev. 1
-ii
Freescale Semiconductor
Preliminary—Subject to Change Without Notice