MCIMX233CJM4B Datasheet, PDF (532/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

AHB-to-APBX Bridge with DMA
DESCRIPTION:
This register holds a pointer to the data buffer in system memory. After the command values have been
read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin,
to or from the buffer pointed to by this register.
EXAMPLE:
Empty example.
11.5.31 APBX DMA Channel 3 Semaphore Register Description
The APBX DMA Channel 3 semaphore register is used to synchronize between the CPU instruction
stream and the DMA chain processing state.
HW_APBX_CH3_SEMA
0x290
Table 11-64. HW_APBX_CH3_SEMA
33222222222211111111110000000000
10987654321098765432109876543210
Table 11-65. HW_APBX_CH3_SEMA Bit Field Descriptions
BITS
31:24 RSVD2
23:16 PHORE
LABEL
15:8 RSVD1
7:0 INCREMENT_SEMA
RW RESET
RO 0x0
RO 0x0
RO 0x0
RW 0x00
DEFINITION
Reserved, always set to zero.
This read-only field shows the current (instantaneous)
value of the semaphore counter.
Reserved, always set to zero.
The value written to this field is added to the
semaphore count in an atomic way such that
simultaneous software adds and DMA hardware
substracts happening on the same clock are protected.
This bit field reads back a value of 0x00. Writing a
value of 0x02 increments the semaphore count by two,
unless the DMA channel decrements the count on the
same clock, then the count is incremented by a net
one.
DESCRIPTION:
Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and
the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore
which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until
software increments the semaphore count.
11-40
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor