MCIMX233CJM4B Datasheet, PDF (1512/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

Digital Video Encoder Programmers’ Manual
38.4 Function and Programming of Controls
38.4.1 Register 0
In register 0, H_cnfg_s[9:0], contains the following signals:
fsync_enbl = H_cnfg_s[9],
fsync_phs = H_cnfg_s[8],
hsync_phs = H_cnfg_s[7],
vsync_phs = H_cnfg_s[6],
T_SYNC_MODE = H_cnfg_s[5:3];
T_ENCD_MODE = H_cnfg_s[2:0].
T_ENCD_MODE identifies the video mode:
000: NTSC-M Mode
001: PAL-B Mode
010: PAL-M Mode
011: PAL-N Mode
100: PAL-CN Mode
101: NTSC with 700:300 scaling on "G"
110: PAL-60 Mode
111: NTSC progressive
T_SYNC_MODE identifies the manner in which the input is synchronized to the display
000: Ext slave: 8-bit Y/C in, SYNC in
001: Ext slave: 16-bit Y/C in, SYNC in
010: Master: 8-bit Y/C in, SYNC out
011: Master: 16-bit Y/C in, SYNC out
1xx: D1 mode: 8-bit Y/C in, SYNC out
In external-sync (“slave”) mode, the rising edge of an external P_HSYNC_IN is used to derive the
horizontal sync for the DVE block if hsync_phs = 0; otherwise the falling edge is used.. Similarly
vsync_phs, selects the active edge of P_VSYNC_IN to generate the internal vertical timing in external
sync mode. The actual horizontal reset is delayed relative to the designated edge of P_HSYNC_IN by
H_HSO cycles of the 27-MHz clock, and the vertical reset is delayed by H_VSO lines relative to
P_VSYNC_IN. (H_HSO and H_VSO are in register 2.) (In D1 mode, horizontal sync is taken from the
leading edge of EAV and vertical sync from that of SFB. H_HSO and H_VSO are not used to delay the
horizontal and vertical resets in this case.)
38-10
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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