MCIMX233CJM4B Datasheet, PDF (1108/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

Pulse-Width Modulator (PWM) Controller
Table 24-16. HW_PWM_ACTIVE3 Bit Field Descriptions
BITS
LABEL
31:16 INACTIVE
15:0 ACTIVE
RW RESET
RW 0x0
RW 0x0
DEFINITION
Number of divided XTAL clock cycles to count from the
beginning of the period before changing the output
from the active state to the inactive state. The internal
count of the channel is compared for greater than this
value to change to the inactive state.
Number of divided XTAL clock cycles to count from the
beginning of the period before changing the output to
the active state. The internal count of the channel is
compared for greater than this value to change to the
active state.
DESCRIPTION:
This register contains the active time and inactive time programming parameters for Channel 3.
EXAMPLE:
HW_PWM_ACTIVEn_WR(3, 0x000000ff); // Set active and inactive counts
24.4.9 PWM Channel 3 Period Register Description
The PWM Channel 3 Period Register specifies the multi-chip attachment mode, clock divider value, active
high, low values and period.
HW_PWM_PERIOD3
HW_PWM_PERIOD3_SET
HW_PWM_PERIOD3_CLR
HW_PWM_PERIOD3_TOG
0x080
0x084
0x088
0x08C
Table 24-17. HW_PWM_PERIOD3
33222222222211111111110000000000
10987654321098765432109876543210
Table 24-18. HW_PWM_PERIOD3 Bit Field Descriptions
BITS
LABEL
31:25 RSRVD2
24 MATT_SEL
23 MATT
RW RESET
RO 0x0
RW 0x0
RW 0x0
DEFINITION
Reserved.
Multichip Attachment Mode clock select. When the
MATT bit is asserted this bit selects which clock to
output. 0: 32 kHz, 1: 24 MHz.
Multichip Attachment mode. This bit overrides the
normal signal generation parameters and enables
either the 24 MHz or 32 kHz crystal clock on the
PWM3 output pin for inter-chip signaling.
24-14
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor