MCIMX233CJM4B Datasheet, PDF (1181/1612 Pages) Freescale Semiconductor, Inc – i.MX23 Applications Processor Reference Manual

EXAMPLE:
No Example.
Debug UART
27.3.13 UART Interrupt Clear Register Description
The ICR register is the Interrupt Clear Register and is write-only. On a write of 1, the corresponding
interrupt is cleared. A write of 0 has no effect.
HW_UARTDBGICR
0x044
Table 27-26. HW_UARTDBGICR
33222222222211111111110000000000
10987654321098765432109876543210
Table 27-27. HW_UARTDBGICR Bit Field Descriptions
BITS
LABEL
31:16 UNAVAILABLE
15:11 RESERVED
10 OEIC
9
BEIC
8
PEIC
7
FEIC
6
RTIC
5
TXIC
4
RXIC
3
DSRMIC
2
DCDMIC
1
CTSMIC
0
RIMIC
RW RESET
RO 0x0
RO 0x0
W 0x0
O
W 0x0
O
W 0x0
O
W 0x0
O
W 0x0
O
W 0x0
O
W 0x0
O
W 0x0
O
W 0x0
O
W 0x0
O
W 0x0
O
DEFINITION
The UART IP only implements 16 and 8-bit registers,
so the top 2 or 3 bytes of every 32-bit register are
always unavailable.
Reserved, read as zero, do not modify.
Overrun Error Interrupt Clear.
Break Error Interrupt Clear.
Parity Error Interrupt Clear.
Framing Error Interrupt Clear.
Receive Timeout Interrupt Clear.
Transmit Interrupt Clear.
Receive Interrupt Clear.
nUARTDSR Modem Interrupt Clear.
nUARTDCD Modem Interrupt Clear.
nUARTCTS Modem Interrupt Clear.
nUARTRI Modem Interrupt Clear.
Freescale Semiconductor
i.MX23 Applications Processor Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
27-17