MC68HC705KJ1 Datasheet, PDF (82/108 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Multifunction Timer Module
RT1 and RT0 — Real-Time Interrupt Select Bits
These read/write bits select one of four real-time interrupt rates, as shown in Table 9-1. Because the
selected RTI output drives the COP watchdog, changing the real-time interrupt rate also changes the
counting rate of the COP watchdog. Reset sets RT1 and RT0.
NOTE
Changing RT1 and RT0 when a COP timeout is imminent can cause a
real-time interrupt request to be missed or an additional real-time interrupt
request to be generated. To prevent this occurrence, clear the COP timer
before changing RT1 and RT0.
RT1:RT0
00
01
10
11
Table 9-1. Real-Time Interrupt Rate Selection
RTI Rate
RTI Period
(f_OP = 2 MHz)
COP Timeout Period
(–0/+1 RTI Period)
f_OP ÷ 2¹⁴
f_OP ÷ 2¹⁵
f_OP ÷ 2¹⁶
f_OP ÷ 2¹⁷
8.2 ms
16.4 ms
32.8 ms
65.5 ms
8 x RTI Period
8 x RTI Period
8 x RTI Period
8 x RTI Period
Minimum COP Timeout
Period
(f_OP = 2 MHz)
65.5 ms
131.1 ms
262.1 ms
524.3 ms
9.5.2 Timer Counter Register
A 15-stage ripple counter is the core of the timer. The value of the first eight stages is readable at any
time from the read-only timer counter register shown in Figure 9-4.
Address:
Read:
Write:
Reset:
$0009
Bit 7
TCR7
0
6
TCR6
5
TCR5
4
TCR4
3
TCR3
2
TCR2
0
0
0
0
0
= Unimplemented
Figure 9-4. Timer Counter Register (TCR)
1
TCR1
0
Bit 0
TCR0
0
Power-on clears the entire counter chain and the internal clock begins clocking the counter. After 4064
cycles (or 16 cycles if the SOSCD bit in the mask option register is set), the power-on reset circuit is
released, clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer interrupt every 1024 internal clock
cycles.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
82
Freescale Semiconductor