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MC68HC705KJ1 Datasheet, PDF (74/108 Pages) Motorola, Inc – HCMOS Microcontroller Unit
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Resets and Interrupts
IRQ
PA3
PA2
PA1
PA0
PIRQ
(MOR)
LEVEL-SENSITIVE TRIGGER
(MOR LEVEL BIT)
VDD
D IRQ Q
LATCH
CK
CLR
IRQF
IRQE
TO BIH & BIL
INSTRUCTION
PROCESSING
EXTERNAL
INTERRUPT
REQUEST
RESET
IRQ VECTOR FETCH
IRQR
Figure 8-4. External Interrupt Logic
EXT. INT. PIN
tILIL
tILIH
EXT.
INT.
.
PIN1
tILIH
.
.
EXT. INT. PINn
IRQ
(INTERNAL)
Figure 8-5. External Interrupt Timing
Table 8-2. External Interrupt Timing (VDD = 5.0 Vdc)(1)
Characteristic
Symbol
Min
Max Unit
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
tILIH
125
—
ns
tILIL
Note(2)
—
tcyc
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted.
2. The minimum tILIL should not be less than the number of interrupt service routine cycles plus 19 tcyc.
Table 8-3. External Interrupt Timing (VDD = 3.3 Vdc)(1)
Characteristic
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
Symbol
tILIH
tILIL
Min
250
Note(2)
Max
—
—
Unit
ns
tcyc
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +85°C unless otherwise noted.
2. The minimum tILIL should not be less than the number of interrupt service routine cycles plus 19 tcyc.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
74
Freescale Semiconductor
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