MC68HC705KJ1 Datasheet, PDF (63/108 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Chapter 7
Parallel I/O Ports (PORTS)
7.1 Introduction
Ten bidirectional pins form one 8-bit input/output (I/O) port and one 2-bit I/O port. All the bidirectional port
pins are programmable as inputs or outputs.
NOTE
Connect any unused I/O pins to an appropriate logic level, either V_DD or
V_SS. Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
Addr.
Register Name:
Bit 7
6
5
4
3
2
1
Bit 0
Port A Data Register (POR- ^Read: _PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
$0000
TA) Write:
See page 64. _Reset:
Unaffected by reset
Port B Data Register ^Read:
0
0
$0001
(PORTB) Write:
See page 66. _Reset:
See Note
PB3
PB2
Unaffected by reset
See Note
$0004
Data Direction Register A ^Read:
(DDRA) Write:
See page 64. _Reset:
DDRA7
0
DDRA6
0
DDRA5
0
DDRA4
0
DDRA3
0
DDRA2
0
DDRA1
0
DDRA0
0
Data Direction Register B ^Read:
0
0
$0005
(DDRB) Write:
See Note
DDRB3 DDRB2
See Note
See page 67. _Reset:
0
0
0
0
0
0
0
0
$0010
Port A Pulldown Register ^Read:
(PDRA) Write:
See page 65. _Reset:
PDIA7
0
PDIA6
0
PDIA5
0
PDIA4
0
PDIA3
0
PDIA2
0
PDIA1
0
PDIA0
0
$0011
Port B Pulldown Register ^Read:
(PDRB) Write:
See page 68. _Reset:
See Note
0
0
PDIB3
0
PDIB2
0
See Note
0
0
= Unimplemented
Note:
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are available for read/write but are not
available externally. Configuring them as inputs will ensure that the pulldown devices are enabled, thus properly termi-
nating them.
Figure 7-1. Parallel I/O Port Register Summary
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
63