MC68HC705KJ1 Datasheet, PDF (28/108 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Memory
SWAIT — Stop-to-Wait Conversion Bit
The SWAIT bit enables halt mode. When the SWAIT bit is set, the CPU interprets the STOP instruction
as a WAIT instruction, and the MCU enters halt mode. Halt mode is the same as wait mode, except
that an oscillator stabilization delay of 1 to 4064 t_cyc occurs after exiting halt mode.
1 = Halt mode enabled
0 = Halt mode not enabled
SWPDI — Software Pulldown Inhibit Bit
The SWPDI bit inhibits software control of the I/O port pulldown devices. The SWPDI bit overrides the
pulldown inhibit bits in the port pulldown inhibit registers.
1 = Software pulldown control inhibited
0 = Software pulldown control not inhibited
PIRQ — Port A External Interrupt Bit
The PIRQ bit enables the PA0–PA3 pins to function as external interrupt pins.
1 = PA0–PA3 enabled as external interrupt pins
0 = PA0–PA3 not enabled as external interrupt pins
LEVEL —External Interrupt Sensitivity Bit
The LEVEL bit controls external interrupt triggering sensitivity.
1 = External interrupts triggered by active edges and active levels
0 = External interrupts triggered only by active edges
COPEN — COP Enable Bit
The COPEN bit enables the COP watchdog.
1 = COP watchdog enabled
0 = COP watchdog disabled
2.9 EPROM Programming Characteristics
Table 2-1. EPROM Programming Characteristics⁽¹⁾
Programming Voltage
IRQ/V_PP
Programming Current
IRQ/V_PP
Programming Time
Per Array Byte
MOR
Characteristic
1. V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = –40°C to +85°C
Symbol
Min
Typ
V_PP
16.0 16.5
I_PP
—¦
3.0
t_EPGM
4
—
t_MPGM
4
—
Max
Unit
17.0
V
10.0
mA
—
ms
—
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
28
Freescale Semiconductor