MC68HC705KJ1 Datasheet, PDF (52/108 Pages) Motorola, Inc – HCMOS Microcontroller Unit

External Interrupt Module (IRQ)
IRQ
PA3
PA2
PA1
PA0
PIRQ
(MOR)
LEVEL-SENSITIVE TRIGGER
(MOR LEVEL BIT)
V_DD
D ^IRQ Q
LATCH
CK
CLR
IRQF
IRQE
TO BIH & BIL
INSTRUCTION
PROCESSING
EXTERNAL
INTERRUPT
REQUEST
RESET
IRQ VECTOR FETCH
IRQR
Figure 5-1. IRQ Module Block Diagram
Addr.
$000A
Register Name
IRQ Status and Control
Register (ISCR)
See page 54.
Read:
Write:
Reset:
Bit 7
IRQE
1
6
5
0
0
0
0
= Unimplemented
4
3
2
0
IRQF
0
R
0
0
0
R = Reserved
Figure 5-2. IRQ Module I/O Register Summary
1
Bit 0
0
0
IRQR
0
0
If edge-sensitive-only triggering is selected, a falling edge on the IRQ/V_PP pin latches an external interrupt
request. A subsequent external interrupt request can be latched only after the voltage level on the
IRQ/V_PP pin returns to logic 1 and then falls again to logic 0.
The IRQ/V_PP pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The
voltage on this pin can affect the mode of operation and should not exceed V_DD.
5.3.2 Optional External Interrupts
The inputs for the lower four bits of port A (PA0–PA3) can be connected to the IRQ pin input of the CPU
if enabled by the PIRQ bit in the mask option register. This capability allows keyboard scan applications
where the transitions or levels on the I/O pins will behave the same as the IRQ/V_PP pin except for the
inverted phase (logic 1, rising edge). The active state of the IRQ/V_PP pin is a logic 0 (falling edge).
The PA0–PA3 pins are selected as a group to function as IRQ interrupts and are enabled by the IRQE bit
in the IRQ status and control register. The PA0–PA3 pins can be positive-edge triggered only or
positive-edge and high-level triggered.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
52
Freescale Semiconductor