MC68HC705KJ1 Datasheet, PDF (55/108 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Timing
The STOP and WAIT instructions set the IRQE bit so that an external interrupt can bring the MCU out of
these low-power modes. In addition, reset sets the I bit which masks all interrupt sources.
5.5 Timing
t_ILIL
IRQ/V_PP PIN
t_ILIH
IRQ₁
t_ILIH
.
.
.
IRQ_n
IRQ (INTERNAL)
Figure 5-5. External Interrupt Timing
Table 5-1. External Interrupt Timing (V_DD = 5.0 Vdc)⁽¹⁾
Characteristic
Symbol
Min
Max
IRQ Interrupt Pulse Width Low (Edge-Triggered)
t_ILIH
1.5
—
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered)
t_ILIH
1.5
Note⁽³⁾
PA0–PA3 Interrupt Pulse Width High (Edge-Triggered)
PA0–PA3 Interrupt Pulse Width High (Edge- and Level-Triggered)
t_ILIL
1.5
—
t_ILIH
1.5
Note⁽³⁾
1. V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = –40°C to + 85°C, unless otherwise noted.
2. t_cyc = 1/f_OP; f_OP = f_OSC/2.
3. The minimum t_ILIL should not be less than the number of interrupt service routine cycles plus 19 t_cyc.
Table 5-2. External Interrupt Timing (V_DD = 3.3 Vdc)⁽¹⁾
Characteristic
Symbol
Min
Max
IRQ Interrupt Pulse Width Low (Edge-Triggered)
t_ILIH
1.5
—
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered)
PA0–PA3 Interrupt Pulse Width High (Edge-Triggered)
PA0–PA3 Interrupt Pulse Width High (Edge- and Level-Triggered)
t_ILIH
1.5
Note⁽³⁾
t_ILIL
1.5
—
t_ILIH
1.5
Note⁽³⁾
1. V_DD = 3.3 Vdc ± 10%, V_SS = 0 Vdc, T_A = –40°C to + 85°C, unless otherwise noted.
2. t_cyc = 1/f_OP; f_OP = f_OSC/2.
3. The minimum t_ILIL should not be less than the number of interrupt service routine cycles plus 19 t_cyc.
Unit
t_cyc(2)
t_cyc
t_cyc
t_cyc
Unit
t_cyc(2)
t_cyc
t_cyc
t_cyc
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
55