MC68HC705KJ1 Datasheet, PDF(40/108 Page) Motorola, Inc

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MC68HC705KJ1 Datasheet, PDF (40/108 Pages) Motorola, Inc – HCMOS Microcontroller Unit

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Central Processor Unit (CPU)

4.6.2.2 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify its contents, and write the modified value

back to the memory location or to the register.

NOTE

Do not use read-modify-write instructions on registers with write-only bits.

Table 4-2. Read-Modify-Write Instructions

Instruction

Mnemonic

Arithmetic Shift Left (Same as LSL)

ASL

Arithmetic Shift Right

ASR

Bit Clear

BCLR(1)

Bit Set

BSET(1)

Clear Register

CLR

Complement (Oneâs Complement)

COM

Decrement

DEC

Increment

INC

Logical Shift Left (Same as ASL)

LSL

Logical Shift Right

LSR

Negate (Twoâs Complement)

NEG

Rotate Left through Carry Bit

ROL

Rotate Right through Carry Bit

ROR

Test for Negative or Zero

TST(2)

1. Unlike other read-modify-write instructions, BCLR and

BSET use only direct addressing.

2. TST is an exception to the read-modify-write sequence

because it does not write a replacement value.

4.6.2.3 Jump/Branch Instructions

Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The

unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register

operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter

when a test condition is met. If the test condition is not met, the branch is not performed.

The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first

256 memory locations. These 3-byte instructions use a combination of direct addressing and relative

addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte

is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the

program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of

the opcode. The span of branching is from â128 to +127 from the address of the next location after the

MC68HC705KJ1 â¢ MC68HRC705KJ1 â¢ MC68HLC705KJ1 Data Sheet, Rev. 4.1

Freescale Semiconductor

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