MC68HC705KJ1 Datasheet, PDF (67/108 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Port B
7.3.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input or an output.
Address:
Read:
Write:
Reset:
$0005
Bit 7
0
0
6
5
4
0
See Notes
0
0
0
= Unimplemented
3
DDRB3
0
2
DDRB2
0
1
Bit 0
See Note
0
0
Note:
DDRB5, DDRB4, DDRB1, and DDRB0 should be configured as inputs at all times. These
bits are available for read/write but are not available externally. Configuring them as inputs
will ensure that the pulldown devices are enabled, thus properly terminating them.
Figure 7-7. Data Direction Register B (DDRB)
DDRB[3:2] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[3:2], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 7-8 shows the I/O logic of port B.
READ DDRB
WRITE DDRB
DDRBx
WRITE PORTB
PBx
PBx
READ PORTB
WRITE PDRB
PDRBx
RESET
SWPDI
Figure 7-8. Port B I/O Circuitry
100-µA
PULLDOWN
Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0
disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data latch. When bit DDRBx is a
logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 7-2 summarizes the operation of the port B pins.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
67