MC68HC705KJ1 Datasheet, PDF (68/108 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Parallel I/O Ports (PORTS)
Table 7-2. Port B Pin Operation
Data Direction Bit
0
1
I/O Pin Mode
Input, high-impedance
Output
Accesses to Data Bit
Read
Write
Pin
Latch⁽¹⁾
Latch
Latch
1. Writing affects the data register, but does not affect input.
7.3.3 Pulldown Register B
Pulldown register B inhibits the pulldown devices on port B pins programmed as inputs.
NOTE
If the SWPDI bit in the mask option register is programmed to logic 1, reset
initializes all port B pins as inputs with disabled pulldown devices.
Address: $0011
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
See Note
0
0
PDIB3
0
PDIB2
0
See Note
0
0
= Unimplemented
Note:
These pulldown devices are permanently enabled when PB5, PB4, PB1 and PB0 are con-
figured as inputs.
Figure 7-9. Pulldown Register B (PDRB)
PDIB[3:2] — Pulldown Inhibit B Bits
PDIB[3:2] disable the port B pulldown devices. Reset clears PDIB[3:2].
1 = Corresponding port B pulldown device disabled
0 = Corresponding port B pulldown device not disabled
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
68
Freescale Semiconductor