MC68HC705KJ1 Datasheet, PDF (60/108 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Low-Power Modes
6.3.5.1 STOP
The STOP instruction during EPROM programming clears the EPGM bit in the EPROM programming
register, removing the programming voltage from the EPROM.
6.3.5.2 WAIT
The WAIT instruction has no effect on EPROM/OTPROM operation.
6.4 Data-Retention Mode
In data-retention mode, the MCU retains RAM contents and CPU register contents at V_DD voltages as low
as 2.0 Vdc. The data-retention feature allows the MCU to remain in a low power-consumption state during
which it retains data, but the CPU cannot execute instructions.
To put the MCU in data-retention mode:
1. Drive the RESET pin to logic 0.
2. Lower the V_DD voltage. The RESET pin must remain low continuously during data-retention mode.
To take the MCU out of data-retention mode:
1. Return V_DD to normal operating voltage.
2. Return the RESET pin to logic 1.
6.5 Timing
OSC
(NOTE 1)
t_RL
RESET
IRQ/V_PP
t_ILIH
(NOTE 2)
IRQ/V_PP
(NOTE 3)
OSCILLATOR STABILIZATION DELAY⁽⁵⁾
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
$07FE
(NOTE 4)
$07FE
$07FE
$07FE
$07FE
$07FF
Notes:
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
5. 4064 cycles or 128 cycles, depending on state of SOSCD bit in MOR
RESET OR INTERRUPT
VECTOR FETCH
Figure 6-1. Stop Mode Recovery Timing
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
60
Freescale Semiconductor