MC68HC705KJ1 Datasheet, PDF (72/108 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Resets and Interrupts
8.2.1 Power-On Reset
A positive transition on the V_DD pin generates a power-on reset.
NOTE
The power-on reset is strictly for power-up conditions and cannot be used
to detect drops in power supply voltage.
A 4064-t_cyc (internal clock cycle) delay after the oscillator becomes active allows the clock generator to
stabilize. If any reset source is active at the end of this delay, the MCU remains in the reset condition until
all reset sources are inactive.
V_DD
(NOTE 1)
OSC1 PIN
OSCILLATOR STABILIZATION DELAY⁽²⁾
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
$07FE $07FE $07FE $07FE $07FE $07FE $07FF
INTERNAL
DATA BUS
NEW PCH NEW PCL
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. 4064 cycles or 128 cycles, depending on state of SOSCD bit in MOR
3. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 8-2. Power-On Reset Timing
8.2.2 External Reset
A logic 0 applied to the RESET pin for 1 1/2 t_cyc generates an external reset. A Schmitt trigger senses the
logic level at the RESET pin.
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
$07FE $07FE $07FE $07FE $07FF NEW PC NEW PC
INTERNAL
DATA BUS
t_RL
RESET
NEW
PCH
NEW
PCL
DUMMY
OP
CODE
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 8-3. External Reset Timing
RESET Pulse Width
Table 8-1. External Reset Timing
Characteristic
Symbol
Min
Max
t_RL
1.5
—
Unit
t_cyc
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
72
Freescale Semiconductor