MC68HC705KJ1 Datasheet, PDF (65/108 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Port A
READ DDRA
WRITE DDRA
WRITE PORTA
READ PORTA
DDRAx
PAx
10-mA SINK CAPABILITY
(PINS PA4–PA7 ONLY)
PAx
(PA0–PA3 TO
IRQ MODULE)
WRITE PDRA
PDRAx
RESET
SWPDI
Figure 7-4. Port A I/O Circuitry
100-µA
PULLDOWN
Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0
disables the output buffer.
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data latch. When bit DDRAx is a logic
0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 7-1 summarizes the operation of the port A pins.
Table 7-1. Port A Pin Operation
Data Direction Bit
I/O Pin Mode
0
Input, high-impedance
1
Output
1. Writing affects the data register but does not affect input.
Accesses to Data Bit
Read
Write
Pin
Latch⁽¹⁾
Latch
Latch
7.2.3 Pulldown Register A
Pulldown register A inhibits the pulldown devices on port A pins programmed as inputs.
NOTE
If the SWPDI bit in the mask option register is programmed to logic 1, reset
initializes all port A pins as inputs with disabled pulldown devices.
Address: $0010
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write: PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-5. Pulldown Register A (PDRA)
PDIA[7:0] — Pulldown Inhibit A Bits
PDIA[7:0] disable the port A pulldown devices. Reset clears PDIA[7:0].
1 = Corresponding port A pulldown device disabled
0 = Corresponding port A pulldown device not disabled
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
65