MC9S08DZ60MLF Datasheet, PDF (80/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 5 Resets, Interrupts, and General System Control
5.8.4 System Options Register 1 (SOPT1)
This high page register is a write-once register so only the first write after reset is honored. It can be read
at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to
avoid accidental changes to these sensitive settings. This register should be written during the user’s reset
initialization program to set the desired controls even if the desired settings are the same as the reset
settings.
7
6
5
4
3
2
1
0
R
COPT
W
0
0
0
STOPE
SCI2PS
IICPS
Reset:
1
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-5. System Options Register 1 (SOPT1)
Table 5-5. SOPT1 Register Field Descriptions
Field
Description
7:6
COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with
COPT[1:0] COPCLKS in SOPT2 defines the COP timeout period. See Table 5-6.
5
STOPE
4
SCI2PS
3
IICPS
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
SCI2 Pin Select— This write-once bit selects the location of the RxD2 and TxD2 pins of the SCI2 module.
0 TxD2 on PTF0, RxD2 on PTF1.
1 TxD2 on PTE6, RxD2 on PTE7.
IIC Pin Select— This write-once bit selects the location of the SCL and SDA pins of the IIC module.
0 SCL on PTF2, SDA on PTF3.
1 SCL on PTE4, SDA on PTE5.
Table 5-6. COP Configuration Options
Control Bits
COPCLKS
COPT[1:0]
Clock Source
COP Window¹ Opens
(COPW = 1)
COP Overflow Count
N/A
0:0
N/A
N/A
COP is disabled
0
0:1
1 kHz
N/A
2⁵ cycles (32 ms²)
0
1:0
1 kHz
N/A
2⁸ cycles (256 ms¹)
0
1:1
1 kHz
N/A
2¹⁰ cycles (1.024 s¹)
1
0:1
Bus
6144 cycles
2¹³ cycles
1
1:0
Bus
49,152 cycles
2¹⁶ cycles
1
1:1
Bus
196,608 cycles
2¹⁸ cycles
1 _{Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column}
displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode
(COPW = 1).
2 _{Values shown in milliseconds based on tLPO = 1 ms. See tLPO in the appendix Section A.12.1, “Control Timing,” for the}
tolerance of this value.
MC9S08DZ60 Series Data Sheet, Rev. 4
80
Freescale Semiconductor