MC9S08DZ60MLF Datasheet, PDF (382/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Appendix A Electrical Characteristics
Table A-12. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient) (continued)
Num C
Rating
RMS frequency variation of a single clock cycle
18 T _{measured 625 ns after reference edge.6}
19
T
Maximum frequency variation averaged over
625 ns window.
20 D _{Lock entry frequency tolerance} ⁷
21 D _{Lock exit frequency tolerance} ⁸
Symbol
f_{pll_cycjit_625ns}
f_{pll_maxjit_625ns}
D_lock
D_unl
22 D Lock time - FLL
t_{fll_lock}
Min
—
—
± 1.49
± 4.47
—
23 D Lock time - PLL
Loss of external clock minimum frequency -
24 D RANGE = 0
t_{pll_lock}
f_{loc_low}
—
(3/5) x f_int
Typical
0.566⁴
Max
—
Unit
%f_pll
0.113
—
—
—
—
—
%f_pll
± 2.98
%
± 5.97
%
t_{fll_acquire+}
1075(1/^fint_t)
s
t_{pll_acquire+}
1075(1/^fpll_ref)
s
—
—
kHz
Loss of external clock minimum frequency -
25 D RANGE = 1
f_{loc_high}
(16/5) x f_int
—
—
kHz
1 _{TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).}
2 _{This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or}
changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the
reference, this specification assumes it is already running.
3 _{This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled}
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it
is already running.
4 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V_DD and V_SS and variation in crystal oscillator frequency increase the C_Jitter percentage for
a given interval. Jitter measurements are based upon a 40MHz MCGOUT clock frequency.
5 _{In some specifications, this value is described as “long term accuracy of PLL output clock (averaged over 2 ms)” with symbol}
“f_{pll_jitter_2ms}.” The parameter is unchanged, but the description has been changed for clarification purposes.
6 _{In some specifications, this value is described as “Jitter of PLL output clock measured over 625 ns” with symbol}
“f_{pll_jitter_625ns}.” The parameter is unchanged, but the description has been changed for clarification purposes.
7 _{Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the}
MCG is already in lock, then the MCG may stay in lock.
8 _{Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.}
MC9S08DZ60 Series Data Sheet, Rev. 4
382
Freescale Semiconductor