MC9S08DZ60MLF Datasheet, PDF (242/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
Table 12-24. Message Buffer Organization
Offset
Address
Register
0x00X0 Identifier Register 0
0x00X1 Identifier Register 1
0x00X2 Identifier Register 2
0x00X3 Identifier Register 3
0x00X4 Data Segment Register 0
0x00X5 Data Segment Register 1
0x00X6 Data Segment Register 2
0x00X7 Data Segment Register 3
0x00X8 Data Segment Register 4
0x00X9 Data Segment Register 5
0x00XA Data Segment Register 6
0x00XB Data Segment Register 7
0x00XC
0x00XD
0x00XE
0x00XF
Data Length Register
Transmit Buffer Priority Register¹
Time Stamp Register (High Byte)²
Time Stamp Register (Low Byte)³
1 _{Not applicable for receive buffers}
2 _{Read-only for CPU}
3 _{Read-only for CPU}
Access
Figure 12-23 shows the common 13-byte data structure of receive and transmit buffers for extended
identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 12-24.
All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation¹.
All reserved or unused bits of the receive and transmit buffers always read ‘x’.
1. Exception: The transmit priority registers are 0 out of reset.
MC9S08DZ60 Series Data Sheet, Rev. 4
242
Freescale Semiconductor