MC9S08DZ60MLF Datasheet, PDF (174/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
Table 10-1. ADC Channel Assignment
ADCH
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
Channel
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
Input
PTA0/ADP0/MCLK
PTA1/ADP1/ACMP1+
PTA2/ADP2/ACMP1P-
PTA3/ADP3/ACMP1O
PTA4/ADP4
PTA5/ADP5
PTA6/ADP6
PTA7/ADP7
PTB0/ADP8
PTB1/ADP9
PTB2/ADP10
PTB3/ADP11
PTB4/ADP12
PTB5/ADP13
PTB6/ADP14
10.1.3 Alternate Clock
ADCH
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000–
11001
11010
11011
11100
11101
11110
Channel
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24 through AD25
AD26
AD27
Reserved
V_REFH
V
Input
PTB7/ADP15
PTC0/ADP16
PTC1/ADP17
PTC2/ADP18
PTC3/ADP19
PTC4/ADP20
PTC5/ADP21
PTC6/ADP22
PTC7/ADP23
Reserved
Temperature Sensor¹
Internal Bandgap²
Reserved
V_REFH
V
The ADC module is capable of performing conversions using the MCU bus clock, the bus clock divided
by two, the local asynchronous clock (ADACK) within the module, or the alternate clock, ALTCLK. The
alternate clock for the MC9S08DZ60 Series MCU devices is the external reference clock (MCGERCLK).
The selected clock source must run at a frequency such that the ADC conversion clock (ADCK) runs at a
frequency within its specified range (f_ADCK) after being divided down from the ALTCLK input as
determined by the ADIV bits.
ALTCLK is active while the MCU is in wait mode provided the conditions described above are met. This
allows ALTCLK to be used as the conversion clock source for the ADC while the MCU is in wait mode.
ALTCLK cannot be used as the ADC conversion clock source while the MCU is in either stop2 or stop3.
10.1.4 Hardware Trigger
The ADC hardware trigger, ADHWT, is the output from the real time counter (RTC). The RTC counter
can be clocked by either MCGERCLK or a nominal 1 kHz clock source.
The period of the RTC is determined by the input clock frequency, the RTCPS bits, and the RTCMOD
register. When the ADC hardware trigger is enabled, a conversion is initiated upon an RTC counter
overflow.
The RTC can be configured to cause a hardware trigger in MCU run, wait, and stop3.
MC9S08DZ60 Series Data Sheet, Rev. 4
174
Freescale Semiconductor