MC9S08DZ60MLF Datasheet, PDF (243/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
Register
Name
R
IDR0
W
R
IDR1
W
R
IDR2
W
R
IDR3
W
R
DSR0
W
R
DSR1
W
R
DSR2
W
R
DSR3
W
R
DSR4
W
R
DSR5
W
R
DSR6
W
R
DSR7
W
R
DLR
W
Bit 7
ID28
ID20
ID14
ID6
DB7
DB7
DB7
DB7
DB7
DB7
DB7
DB7
6
ID27
ID19
ID13
ID5
DB6
DB6
DB6
DB6
DB6
DB6
DB6
DB6
5
ID26
4
ID25
3
ID24
ID18
SRR⁽¹⁾
IDE⁽¹⁾
2
ID23
ID17
1
ID22
ID16
Bit0
ID21
ID15
ID12
ID11
ID10
ID9
ID4
ID3
ID2
ID1
ID8
ID7
ID0
RTR²
DB5
DB4
DB3
DB2
DB1
DB0
DB5
DB4
DB3
DB2
DB1
DB0
DB5
DB4
DB3
DB2
DB1
DB0
DB5
DB4
DB3
DB2
DB1
DB0
DB5
DB4
DB3
DB2
DB1
DB0
DB5
DB4
DB3
DB2
DB1
DB0
DB5
DB4
DB3
DB2
DB1
DB0
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
= Unused, always read ‘x’
Figure 12-23. Receive/Transmit Message Buffer — Extended Identifier Mapping
1 _{SRR and IDE are both 1s.}
2 _{The position of RTR differs between extended and standard indentifier mapping.}
Read: For transmit buffers, anytime when TXEx flag is set (see Section 12.3.6, “MSCAN Transmitter Flag
Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
243