MC9S08DZ60MLF Datasheet, PDF (108/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 6 Parallel Input/Output Control
6.5.6 Port F Registers
Port F is controlled by the registers listed below.
6.5.6.1 Port F Data Register (PTFD)
R
W
Reset:
7
PTFD7
0
6
PTFD6
5
PTFD5
4
PTFD4
3
PTFD3
2
PTFD2
0
0
0
0
0
Figure 6-37. Port F Data Register (PTFD)
Table 6-35. PTFD Register Field Descriptions
1
PTFD1
0
0
PTFD0
0
Field
Description
7:0
PTFD[7:0]
Port F Data Register Bits — For port F pins that are inputs, reads return the logic level on the pin. For port F
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port F pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
6.5.6.2 Port F Data Direction Register (PTFDD)
R
W
Reset:
7
PTFDD7
0
6
PTFDD6
5
PTFDD5
4
PTFDD4
3
PTFDD3
2
PTFDD2
0
0
0
0
0
Figure 6-38. Port F Data Direction Register (PTFDD)
Table 6-36. PTFDD Register Field Descriptions
1
PTFDD1
0
0
PTFDD0
0
Field
Description
7:0
PTFDD[7:0]
Data Direction for Port F Bits — These read/write bits control the direction of port F pins and what is read for
PTFD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn.
MC9S08DZ60 Series Data Sheet, Rev. 4
108
Freescale Semiconductor