MC9S08DZ60MLF Datasheet, PDF (37/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 3 Modes of Operation
3.6 Stop Modes
One of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in SOPT1
register is set. In both stop modes, all internal clocks are halted. The MCG module can be configured to
leave the reference clocks running. See Chapter 8, “Multi-Purpose Clock Generator (S08MCGV1),” for
more information.
Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various
conditions. The selected mode is entered following the execution of a STOP instruction.
Table 3-1. Stop Mode Selection
STOPE ENBDM ¹ LVDE LVDSE PPDC
Stop Mode
0
x
1
1
x
x Stop modes disabled; illegal opcode reset if STOP instruction executed
x
x Stop3 with BDM enabled ²
1
0
Both bits must be 1 x Stop3 with voltage regulator active
1
0
Either bit a 0
0 Stop3
1
0
Either bit a 0
1 Stop2
1 _{ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see Section 17.4.1.1, “BDC Status and}
Control Register (BDCSCR)”.
2 _{When in Stop3 mode with BDM enabled, The SIDD will be near RIDD levels because internal clocks are enabled.}
3.6.1 Stop3 Mode
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Exit from stop3 is done by asserting RESET or an asynchronous interrupt pin. The asynchronous interrupt
pins are IRQ, PIA0–PIA7, PIB0–PIB7, and PID0–PID7. Exit from stop3 can also be done by the
low-voltage detect (LVD) reset, low-voltage warning (LVW) interrupt, ADC conversion complete
interrupt, real-time clock (RTC) interrupt, MSCAN wake-up interrupt, or SCI receiver interrupt.
If stop3 is exited by means of the RESET pin, the MCU will be reset and operation will resume after
fetching the reset vector. Exit by means of an interrupt will result in the MCU fetching the appropriate
interrupt vector.
3.6.1.1 LVD Enabled in Stop3 Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.
For the ADC to operate the LVD must be left enabled when entering stop3.
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
37