MC9S08DZ60MLF Datasheet, PDF (222/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
12.1.3 Block Diagram
Oscillator Clock
Bus Clock
MSCAN
CANCLK
Tq Clk
MUX
Presc.
Receive/
Transmit
Engine
RXCAN
TXCAN
Transmit Interrupt Req.
Receive Interrupt Req.
Errors Interrupt Req.
Wake-Up Interrupt Req.
Control
and
Status
Configuration
Registers
Message
Filtering
and
Buffering
Wake-Up
Low Pass Filter
Figure 12-2. MSCAN Block Diagram
12.2 External Signal Description
The MSCAN uses two external pins:
12.2.1 RXCAN — CAN Receiver Input Pin
RXCAN is the MSCAN receiver input pin.
12.2.2 TXCAN — CAN Transmitter Output Pin
TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the
CAN bus:
0 = Dominant state
1 = Recessive state
12.2.3 CAN System
A typical CAN system with MSCAN is shown in Figure 12-3. Each CAN node is connected physically to
the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current
needed for the CAN bus and has current protection against defective CAN or defective nodes.
MC9S08DZ60 Series Data Sheet, Rev. 4
222
Freescale Semiconductor