MC9S08DZ60MLF Datasheet, PDF (184/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
Table 10-6. ADCCFG Register Field Descriptions (continued)
Field
3:2
MODE
1:0
ADICLK
Description
Conversion Mode Selection. MODE bits are used to select between 12-, 10-, or 8-bit operation. See Table 10-8.
Input Clock Select. ADICLK bits select the input clock source to generate the internal clock ADCK. See
Table 10-9.
ADIV
00
01
10
11
Table 10-7. Clock Divide Select
Divide Ratio
1
2
4
8
Clock Rate
Input clock
Input clock ÷ 2
Input clock ÷ 4
Input clock ÷ 8
MODE
00
01
10
11
Table 10-8. Conversion Modes
Mode Description
8-bit conversion (N=8)
12-bit conversion (N=12)
10-bit conversion (N=10)
Reserved
ADICLK
00
01
10
11
Table 10-9. Input Clock Select
Selected Clock Source
Bus clock
Bus clock divided by 2
Alternate clock (ALTCLK)
Asynchronous clock (ADACK)
10.3.8 Pin Control 1 Register (APCTL1)
The pin control registers disable the I/O port control of MCU pins used as analog inputs. APCTL1 is
MC9S08DZ60 Series Data Sheet, Rev. 4
184
Freescale Semiconductor