MC9S08DZ60MLF Datasheet, PDF (25/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features

Chapter 1 Device Overview
1 kHZ
LPO
MCGERCLK
MCGIRCLK
TPM1CLK TPM2CLK
RTC
COP TPM1
TPM2
IIC
SCI1
SCI2
SPI
MCGFFCLKVALID
MCG
MCGFFCLK
÷2
1
0
MCGOUT
MCGLCLK
÷2 ^BUSCLK
FFCLK*
XOSC
CPU
BDC
ADC
MSCAN FLASH EEPROM
EXTAL XTAL
* The fixed frequency clock (FFCLK) is internally
synchronized to the bus clock and must not exceed one half
of the bus clock frequency.
ADC has min and
max frequency
requirements.See
the ADC chapter and
electricals appendix
for details.
Figure 1-2. MC9S08DZ60 System Clock Distribution Diagram
Flash and
EEPROM have
frequency
requirements for
program and
erase operation.
See the
electricals
appendix for
details.
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
25