W65C832_1 Datasheet, PDF (9/64 Pages) –

WDC
THE WESTERN DESIGN CENTER, INC.
W65C832
INTRODUCTION
The WDC W65C832 is a CMOS 32-bit microprocessor featuring total software
compatibility with their 8-bit NMOS and 8-bit and 16-bit CMOS 6500-series
predecessors. The W65C832 is pin-to-pin compatible with 16-bit devices currently
available. These devices offer the many advantages of CMOS technology I including
increased noise immunity, higher reliability, and greatly reduced power
requirements. A software switch determines whether the processor is in the 8-bit or
16-bit "emulation" mode, or in the native mode, thus allowing existing systems to
use the expanded features.
As shown in the processor programming model, the Accumulator, ALU, X and Y Index
registers have been extended to 32 bits. A 16-bit Program Counter, Stack Pointer
and Direct Page register augments the Direct Page addressing mode (formerly Zero
Page addressing). Separate Program Bank and Data Bank registers allow 24-bit memory
addressing with segmented or linear addressing for program space and 32-bit 4GByte
data space for ASIC use although only 24 bits of address are available in the
standard pin-out.
Four signals provide the system designer with many options. The ABORT input can
interrupt the currently executing instruction without modifying internal register,
thus allowing virtual memory system design. Valid Data Address (VDA) and Valid
Program Address (VPA) outputs facilitate dual cache memory by indicating w.hether a
data segment or program segment is accessed. Modifying a vector is made easy by
monitoring the Vector Pull (VP) output.
\ KEY FEATURES OF THE W65C832
* ^{Advanced CMOS design for low power * Separate program and data bank}
power consumption and increased
registers allow program
noise immunity
segmentation or full 16-MByte
* ^{Single 1.2-5.25V power supply,}
as specified
linear addressing
* New Direct Register and stack
* ^{Emulation mode allows complete}
relative addressing provides
hardware and software
capability for re-entrant,
compatibility with W65C816 designs re-cursive and re-Iocatable
* ^{24-bit address bus allows access}
to 16 MBytes of memory space
programming
* 24 addressing modes-13 original
* ^{Full 32-bit ALU, Accumulator,}
6502 modes, plus 11 new addressing
and Index Registers
modes with 91 instructions using
* ^{Valid Data Address (VDA) and}
Valid Program Address (VPA)
255 opcodes
* Wait-for-Interrupt (WAI) and
output allows dual cache and
Stop-the Clock (STP) instructions
cycle steal DMA implementation
further reduce power consumption,
* ^{Vector Pull (VP) output indicates}
when interrupt vectors are being
decrease interrupt latency and
allows synchronization with
addressed. May be used to
implement vectored interrupt
external events
* Co-Processor (COP) instruction
design
with associated vector supports
* ^{Abort (ABORT) input and associated co-processor configurations, i.e.,}
vector supports virtual memory
floating point processors
system design
* Block move ability
MARCH 1990
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